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    2,000 e1 vhdl jobs found, pricing in USD

    I'm seeking an experienced and detail-oriented developer to create a Custome PCILeech firmware for SCREAMER PCIE SQUIRREL direct access memory card utilizing the 7 Series FPGA 35t chip. Firmware must...Squirrel. Firmware must bypass and avoid anti-cheat detection on EAC/BE etc. Responsibilities: - Develop firmware for PCILeech FPGA - Debugging and problem-solving throughout firmware development Skills & Experience: - Strong experience in FPGA programming and firmware development - Excellent debugging and problem-solving skills - Experience with high-speed data transmission - Proficiency with VHDL/Verilog languages The timeline for project completion is flexible, indicating a strong emphasis on quality over speed. However, I am eager to commence with the right candidate a...

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    I require the expertise of a skilled freelancer to assist in the configuration of our Sangoma Vega 400g Voice Gateway device. It's critical that you have familiarity with E1 ISDN to SIP trunk conversion, due to our primary objective being system compatibility upgrading. Key responsibilities: - Customize settings on Sangoma Vega 400g Voice Gateway according to specific requirements. - Setting up a connection with Swedish Telco, Telia. Ideal Candidate: - Previous experience with Sangoma Vega Gateway configuration. - Knowledgeable in E1 ISDN to SIP trunk conversions. - Familiar with Telia's connectivity. - Quick and efficient problem solver, without sacrificing quality results.

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    Completing an intermediate-level circuit simulation is on the top of my agenda, and time is of the essence. Key Requirements: - Generate a simulation circuit using either Verilog or VHDL. - The complexity level should be intermediate, meaning that it should include components such as adders, decoders, and multiplexers. Ideal Candidate: An experienced freelancer with a strong background in circuitry and simulation languages such as Verilog or VHDL. Quick response and comprehension of task requirements are paramount due to the urgency of the project. Remember, the successful completion of this project is deemed urgent. Therefore, a prompt response and start are appreciated.

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    I need a VHDL coding expert capable of creating a code for an Intel FPGA that will allow for audio and video output in analog format. The ideal freelancer will: - Be proficient in VHDL, FPGA programming and signal processing - Have a rich experience with Intel FPGA models - Understanding the intricacies of analog audio and video signals This job will require creating a reliable and effective VHDL code that will deliver high-quality audio and video signals to reflect the input accurately. Please bid if you are confident in your ability to deliver this project.

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    Task details - For ISUP/SS7 (E1 card implementation) along with IVR knowledge in any open source SIP servers like Freeswitch/Yate/Mobicents etc. or working experience in CRBT server. Interested candidates please apply

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    We are looking for consultants - Consultant preferred from India. 1) Consultant - SRP Experience in working with development/implementation of SCP and SRF. Experience in handling interfaces of SCP SRF like INAP, SIP, Webservices, Websockets WebRTC (in the context of SCF and S...Mobius JSS7 or any of the varient IVR implementation with Freeswitch on SS7 Knowledge and work experience on YATE SS7 implementation. Anyone with following expereince and skills also may apply Consultant - CRBT worked in CRBT and similar products Having knowledge in the following protocols a) INAP over SIGTRAN/SIP b) SIP/RTP c) ISUP over E1 3) M3UA over SIGTRAN Knowledge on working with Freeswitch/Asterix and IVR solutions Work experience on working on E1 and SIP/RTP call scenarios. Interested can...

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    I am seeking a proficient electronic engineer with an in-depth understanding of VHDL (high level logic design) it's related to xlinx and vivado

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    In this project we will be implementing a control system using the Lattice iCE FPGA. The task at hand involves converting a schematic for a Synchronous Data Link Control (SDLC) data stream to an SPI Master data stream converter to Verilog or VHDL and then verifying the design through simulation. And finally creating the file that will be used to program the target part in production. The ideal freelancer for this job is proficient in working with FPGAs, preferably with a strong background in the Lattice iCE FPGA. I’m looking for someone adept in schematic to HDL conversion. Experience in working with SDLC data will serve as a plus. Please ensure that your experience and skills include: - FPGA development, specifically with the Lattice iCE. - Expertise in schematic to HDL ...

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    We've written some VHDL code for FPGA we need someone to adapt it to our coding standard. we will share a report of all violations for a set of files and the VHDL code shall be modified as specified in the coding standard. To make an example all signals shall be names s_<signal_name>, signal test_sig : std_logic; -- violation! signal s_test_sig : std_logic; -- correct the code will be shared with a Gitlab repo, a dedicatd branch will be created to modify the original code. the code shall be compiled, to chekc no errors were introduced. as soon as the code is delivered we wil rerun the checker to chek for residual errors, and we would provide a feedback (unless the freelancer has the same checker tool)

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    We have an existing VHDL project that implements various memory protocols that runs on a Lattice FPGA (MachXO2 LCMXO2-4000HC). The FPGA is used as a high-speed data bridge between an ARM based microcontroller and a connected memory device (using SMC). This project is to expand the existing project and add support for the eMMC protocol and eMMC Flash memory devices. For testing, we have acquired various 64GB devices that are available on Mouser and DigiKey. Basic functionality is required: reading/writing/erasing with legacy speeds and 1,4,8-bit data bus. Project can be extended to include additional modes / features. The project is in Lattice Diamond, and written in VHDL. All work must be done to the existing project. And tested using exported bitstream binaries. Note: if ...

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    We have an existing VHDL project that implements various memory protocols that runs on a Lattice FPGA (MachXO2 LCMXO2-4000HC). The FPGA is used as a high-speed data bridge between an ARM based microcontroller and a connected memory device (using SMC). This project is to expand the existing project and add support for the eMMC protocol and eMMC Flash memory devices. For testing, we have acquired various 64GB devices that are available on Mouser and DigiKey. Basic functionality is required: reading/writing/erasing with legacy speeds and 1,4,8-bit data bus. Project can be extended to include additional modes / features. The project is in Lattice Diamond, and written in VHDL. All work must be done to the existing project. Note: if you want to make a bid, please respond with yo...

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    ...specifications and performance targets for the graphics card, considering factors such as core count, memory bandwidth, and power efficiency. Designing and modeling the GPU architecture using computer-aided design (CAD) software, incorporating advanced features for rendering, compute, and artificial intelligence. Implementing the design using hardware description languages (HDLs) such as Verilog or VHDL, and simulating the functionality using specialized tools. Conducting rigorous testing, validation, and optimization to ensure the graphics card meets performance, reliability, and compatibility standards. Iterating on the design based on feedback, performance analysis, and emerging technologies. **Power Efficiency:** - My priority is an energy-saving design. The challenge lies i...

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    ...this project. - Familiarity with high-speed interface protocols and their integration into FPGA designs. **Ideal Skills and Experience:** - Strong background in electrical engineering or computer science, with a focus on hardware design. - Prior projects or experience in FPGA-based design, especially those involving DSP or video processing. - Proficient in C/C++ for algorithm development and HDL (VHDL/Verilog) for hardware description. - Knowledge of optimization techniques for power efficiency and performance maximization in FPGA designs. - Ability to work with simulation tools and perform thorough validation and testing of the designed hardware. My project calls for an innovative and technically skilled freelancer who can navigate the complexities of advanced FPGA design. If ...

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    OPEN PROJECT #2401-e1 per messages

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    ...FPGA-based game similar to a classic crossing road game with a twist. Required Skills: - Proficient in VHDL programming - Experience with FPGA design and implementation - Familiar with character movement logic - Ability to implement a scoring system into FPGA projects Project Requirements: - Design VHDL code specifically for an FPGA target device - Develop code that allows character movement within the game - Create a scoring system to track and display the player's score -able to score to reach a target and gameover point -able to control the game using fpga or keyboard - able to connect via vga Ideal Candidate: - You should have a portfolio demonstrating previous work with FPGAs and VHDL. - Experience in game development or simulation is highly desirable...

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    ...freelancer to implement an intermediate System on Chip (SoC) module using VHDL for an FPGA-based system. Key Responsibilities: - Develop and simulate VHDL code for an FPGA-based SoC module. - Ensure code meets functionality and performance requirements. - Provide documentation and support for testing and integration. Ideal Skills: - Proficient in VHDL programming. - Experience with FPGA design and implementation. - Familiar with SoC architecture and digital design principles. - Ability to write clean, optimized, and well-documented code. Qualifications: - Previous projects involving VHDL and FPGAs. - Understanding of intermediate SoC modules. - Good problem-solving and communication skills. Project Deliverables: - Working VHDL code as per specifica...

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    I am looking for an expert in FPGA design who can help create a SmartFusion2 design with specific features. the designer shall be able to - update VHDL design to control other peripherals integrating in the current design - update the SW on the ARM Ideally, the testing function should use predefined test cases. The main focus of the testing system needs to be hardware testing. Therefore, essential skills and experience include knowledge of hardware testing techniques and familiarity with FPGA configuration, power management, and communication protocols.

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    I'm looking for an experienced VHDL developer to create a traffic-themed crossing road game for FPGA, with a keen eye for detail and efficiency in design. Key Responsibilities: - Design and implement a VHDL-based FPGA system - Program player movement controls and responsive gameplay - Develop dynamic obstacle generation mechanics Skills Required: - Proficient in VHDL and FPGA programming - Strong understanding of digital design and signal processing - Experience in gaming or simulation projects preferred The successful freelancer must showcase previous FPGA projects, ideally with gaming applications. Please provide code samples or portfolio links with your proposal.

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    Reference Image Gallery of What I need 3D Modeled. It will be for making a glowing sign/lamp. I would like someone with 3D printing experience or CAD work experience. I only need the Black and Green parts of the model designed. I already have the logo file in 3d model form. I am looking for a very accurate version using the dimensions listed in the drawings I shared with dimensions for a1-b1-c1-d1-e1-f1-g and a2-b2-c2-d2-e2-f2-g as referenced. Reference Images and Video - I require an experienced 3D modeler to create parts for a personal project. Using the reference images provided, you'll be tasked with making a 3D model, suitable for 3D printing. The output I require is the .STL file, logically separating

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    Looking for a shirt designed for E1 Archery products, the website is and i've attached the logo as well as an old shirt design for another business for inspiration, but wanting it to be different to this :) Looking to have the logo on the shirt obviously.

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    I'm seeking a talented individual with a strong background in VHDL and FPGA design, specifically with Altera products, who can successfully implement communication interfaces within my project. The ideal candidate will possess a deep understanding of UART protocol and be capable of integrating it with other interfaces. Requirements: - Proficiency in VHDL programming for FPGA - Experience with Altera FPGA design tools - Successful implementation of UART interfaces - Knowledge in LAN and USB communication The scope of the project includes: - Implementing a low-speed UART interface (up to 115200 bps) - Integrating UART with LAN and USB interfaces on the FPGA The right freelancer will have a strong portfolio demonstrating their expertise in FPGA interface design and commu...

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    ...4x4 matrix and 2x2 kernel convolution. - Employ kogge stone adder for efficiency. - Integrate vedic multiplier for rapid multiplication. - Ensure system operates with integer value precision. - Target design is for an FPGA using Verilog or VHDL. **Ideal Skills** - Proficiency in FPGA programming. - Strong background in digital arithmetic circuits. - Experience with kogge stone adders and vedic multipliers. - Knowledge of image processing techniques. - Use of Shifting , multiplication and addition in performing 2d convolution - Fluent in Verilog or VHDL coding. - Ability to optimize for power, area, and speed. **Project Deliverables** - Optimized HDL code for the convolution system. - Synthesis and simulation results demonstrating performance. - Documentation outlining de...

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    We have an existing VHDL project that implements various memory protocols that runs on a Lattice FPGA (MachXO2). The FPGA is used as a high-speed data bridge between an ARM based microcontroller and a memory device. This project is to expand that to add eMMC support, such as typical 64GB eMMC 5.1 devices available on Digikey/Mouser. Basic functionality is required: reading/writing/erasing with legacy speeds and 1,4,8 bit data bus. Project can be extended to include additional modes / features. Note: if you want to make a bid, please respond with your previous experience with working with eMMC devices.

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    ...consectutively per key No more then 6 number consectutively per key The private keys in the hashtable cant have any of these values in them . This will drastically reduce the scan space Skills and Experience: - Advanced level of familiarity with FPGA and bitstream development - Strong understanding of FPGA architecture and programming languages - Proficiency in programming languages such as VHDL or Verilog - Experience in designing and implementing complex FPGA systems - Knowledge of hardware design principles and methodologies Project Requirements: - Develop a Kangaroo Pollard FPGA Bitstream for personal use - Create an operating application with specific features based on my requirements - Integrate the bitstream and operating application to work seamlessly together - Pro...

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    I have a new broadband supply but am having difficulty setting up the router. The supply is a VDSL type. I have all the information for set up. The supply is live as this was connected last week. However I cannot program the router and need assistance. The property is in Heneage Street, London E1 5AZ. We opted for no phone line, just broadband. BT Openreach activated the service.

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    i am looking for an individual who can do perform the project on Quartus in VHDL formate. We are looking for only experts.

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    I am looking for a skilled software developer to create a...that connects FPGA cards for my temperature measurement equipment. This role involves designing a program that is compatible with the Windows operating system. To develop the connection effectively, a solid knowledge of VHDL, Spartan 3 boards and C++ programming will be required. The ideal developer should be comfortable working with a basic command line interface. The main focus is on functionality, not graphic aesthetics. To be successful, both the functionality and security of the program must be prioritized. Key essentials for the job include: - Deep knowledge of VHDL - Knowledge of Spartan 3 card. - Know C++ programming. - Experience with command line interfaces. - Ability to ensure security and error checkin...

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    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

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    Design a TImestamp generator from PPS and a NMEA parser in VHDL

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    I am looking for a programmer to help me with my project. Programming Language: VHDL Timeframe: ASAP Skills and Experience: - Proficiency in VHDL programming language - Experience in developing and implementing VHDL designs - Familiarity with FPGA programming - Strong problem-solving skills and attention to detail - Ability to work efficiently and meet tight deadlines Project Details: - The project involves developing and implementing VHDL designs for a specific application. - The programmer will be responsible for coding, testing, and debugging the designs. - The project needs to be completed as soon as possible, so the ability to work quickly and efficiently is crucial. If you have experience in VHDL programming and are available to start immediat...

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    Looking for people to attend an online business event via Zoom Requirements: - You are NOT required to speak, you just need to enter the meeting room on Zoom, and have your webcam turned on - Have a working computer with webcam - Smart casual / formal wear - Stay online during the event (1 hour) - Purpose of the event: Networking/Business - Demographic of attendees: General public/Business Professionals Skills and experience preferred: - Experience attending virtual events - Familiarity with Zoom Event: Technology Collaboration between Europe and China Date: 10:00-11:00 (GMT/UK TIME) 30 Nov 2023 *Please check the correct time in your timezone if you live outside United Kingdom Duration: 1 hour GUIDELINE for attendance: 1. Make sure you have already downloaded Zoom and registered an acc...

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    Description: Create a Hardware-Software Codesign version of the k-mean clustering algorithm K-means clustering is a popular data mining algorithm that partitions n samples into k clusters (note: the k-nearest neighbor classifier algorithm used in machine learning can leverage the cluster centers produced by the k-means clustering algori...algorithms have been developed that quickly converge to a local optimum solution. We will consider one of those algorithms in this project. I have provided a C code version of the k-means clustering algorithm, and a Vivado block diagram and memory layout (explained below) that you will use as a starting point. You will need to study the C version and then decide which components to implement as a VHDL module using the BRAM (you also used BRAM in HI...

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    ...of brisk walking steps you have completed so far. * In cell C1, enter "Current Day of the Week" as a header. * In cell C2, enter the current day of the week as an integer (e.g., 4 for Thursday). * In cell D1, enter "Remaining Steps Needed" as a header. * In cell D2, enter the following formula to calculate the remaining steps needed:


Copy code=MAX(0, (7 * 3000) - A2) * 

 * In cell E1, enter "Remaining Days in the Week" as a header. * In cell E2, enter the following formula to calculate the remaining days in the week: Copy code =MAX(0, 7 - C2) * In cell F1, enter "Remaining Brisk Walking Steps Needed" as a header. * In cell F2, enter the following formula to calculate the remaining brisk walking steps needed: Copy code...

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    need to implement neural networks in vhdl. More details will be shared in discussions

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C

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    I'm looking for a Freelancer to help me find out VHDL code for designing crossy road game. I already have a detailed plan that I'd like to have implemented, so I need someone who can understand what I'm looking for and execute the plan quickly and accurately. This is a micro project ,so I need someone who is willing to help me to get a vhdl designing code for crossy road game. If you think you have the expertise to handle a project like this, please reach out to me and let me know how you can help. Thank you for your time and consideration.

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    I am seeking assistance with designing both an ALU and memory modules for my project. I require help with both coding and design aspects. Specific tasks for this project include: - Designing ...assistance with designing both an ALU and memory modules for my project. I require help with both coding and design aspects. Specific tasks for this project include: - Designing an ALU - Designing memory modules Ideal skills and experience for this job include: - Proficiency in VHDL programming language - Strong knowledge and understanding of ALU and memory module design - Experience in both coding and design aspects of similar projects If you have experience in designing ALU and memory modules and are proficient in VHDL programming language, I would like to discuss this project ...

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    I need a softball flyer for a tournament. I am attaching a sample, our logo, two QR codes and our contact information. Below is ...our schedule and teams we are playing. I am looking for something original and eye catching. I need a relatively fast delivery. Please note Sunday is a different location. I will need: -Fully Layered PSD PNG JPG Information: Friday & Saturday Field: Reid Park 701 Orange St Riverside, California 92501 Schedule: Friday - 6:30pm Field 6 vs. Royalty Gold Silva Saturday - 8:00am Field 1 vs. E1 Prospects Garrison/Cabana 9:45am Field 1 vs. OC Batbusters Martin 11:30am Field 1 vs. Nevada Hotshots Gooch Sunday Field: Orange Terrace 20010 Orange Terrace Pkwy Riverside, California 92508 Sunday - 8:00am Field 5 vs. CV Blue Sox Elite R...

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    I am in need of an intermediate FPGA VHDL designer who can assist me with designing a small module. This project requires someone with experience and expertise in VHDL programming for FPGAs. Skills and Experience: - Proficiency in VHDL programming for FPGAs - Experience with designing small modules - Strong understanding of FPGA architecture and design principles The project has a tight deadline, with completion expected within the next 1-2 weeks. Therefore, it is important for the freelancer to be able to work efficiently and deliver high-quality work within this timeframe. If you have the necessary skills and experience in FPGA VHDL design, and are able to meet the project requirements within the specified timeframe, I encourage you to apply for this proj...

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    design of a VHDL synthesizable module to implement data exchange between firmware and software on a KRIA SOM module

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    ...your solution you should write out the null and alternative hypotheses and explain the testing procedure before conducting the corresponding testing procedure; in doing so, follow the discussions from section 3.4 of SW (the reference book of the course). Use a type I error of 5%. 5. E Run a regression of ahe on a constant, age, female and bachelor and provide the regression results (as a table). E1 If age increases from 25 to 26, then how much are earnings expected to change? E2 If age increases from 33 to 34, then how much are earnings expected to change? 6. F Run a regression of ln(ahe) on a constant, age, female and bachelor. F1 If age increases from 25 to 26, then how much are earnings expected to change? F2 If age increases from 33 to 34, then how much are earnings exp...

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    ...degree; C4 males without a bachelor degree; D Run a regression of ahe on a constant, age, female and bachelor and provide the regression results (as a table). D1 If age increases from 25 to 26, then how much are earnings expected to change? D2 If age increases from 33 to 34, then how much are earnings expected to change E Run a regression of ln(ahe) on a constant, age, female and bachelor. E1 If age increases from 25 to 26, then how much are earnings expected to change? E2 If age increases from 33 to 34, then how much are earnings expected to change? F Run a regression of ln(ahe) on a constant, ln(age), female and bachelor. F1 If age increases from 25 to 26, then how much are earnings expected to change? F2 If age increases from 33 to 34, then how much are earnings expec...

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    For this project, am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since the playe...

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    ...assist me with an Axi Ethernet 1G base project for Xilinx KCU116, which is a Kintex Ultrascale. Project MUST NOT CONTAIN Microblaze, only soldi VHDL code. Target Device: Target device is Kintex Ultrascale+, as KCU116 board will be the target device for the project. Intended Functionality: The main objective of this project is to develop a networking solution using Ethernet. The freelancer should be experienced in VHDL developments and in networking functionalities for Xilinx KCU116. Specific Requirements: - 1/2.5GB Axi Ethernet Core (not provided, but free trial is available by Xilinx) based - 1Gb speed required - No Microblaze or MPSoC, only VHDL code. - Configuration must be done by AXI-Lite bus (No Configuration vector) - Ethernet frames must be sent by AXI-St...

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    ...Payments are only placed after proof of work. This is the start of a series of activities, so we intend to keep working with the professional if the work is promptly and well done. Basic Clean up of drawings: - Follow the format for sizes, fonts, purged elements, clean file, - Use Polylines, Circles and MText only, - Use the given Block References only, - Use the given layers only: A1 (Architecture), E1 (Electrical 1), E2 (Electrical 2), Defpoints, 0. Symbolic Clean up of drawings: - Redraw the information into the given format, - Separate and arrange each Single Line Drawing in the Model, as shown in the format - Separate and present each Single Line Drawing into separate Layouts (a total of 18 sheets approx.. for the uploaded drawings), with a requested given Sheet Template...

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    For this project, I am looking to create a system design for the game Beer-Pong using a combination of BASYS 3 and additional components compatible with BASYS 3 and VHDL. I want the system design to have a basic level of complexity with a specified deadline of 3 weeks for completion. Different components like switches, LEDs and sensors. The aim of this project is to design a system for the game Beer-Pong using BASYS 3 and components that are compatible with BASYS 3. In this project, we will be able to play advanced beer- pong. Our setup will consist of 6 cups in total, and the aim is to throw three balls out of 5 into adjacent 3 cups ( Balls must perform a straight line). Thus, at that point, our game differs from the classical game. Positions of the cups can be adjusted since...

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    Create a simple yet effective Smart Home Energy Monitor using your expertise in electrical engineering and FPGA/VHDL. This project aims to help working individuals monitor and optimize their home energy consumption. It can be both fun and practical.

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    We are currectly looking for support to write a simple motor model in VHDL, that will be used to test our motor controller in FPGA. The motor model shall be as simple as possible and an equivalent Matlab/Octave/Python/C/C++ model would be desiderable and used to validate the VHDL model

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    requiring the design of a VHDL synthesizable module to interface an incremental encoder. This is generic ABZ quadrature decoder, some code woulc also be found on the net already, that requires integration and testing () The encoder is the Z is for homing (it marks the zero position of the encoder) specs and deliverables in the attached document

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