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    3,121 verilog vhdl jobs found, pricing in USD
    Electronics design circuit 6 days left
    VERIFIED

    I have some design which are related to electronics. I want these digital design to be solved using vhdl. These task are pretty simple. i will provide you further details as you contact me

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    I need some help which is related to digital design which to be solved using vhdl. These are simple tasks. As you contact i will provide you some details

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    Build a project in system verilog to work as a convolution engine

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    (1) FSM WITH VHDL+ TESTBENCH ( TRUTH TABLE,KMAP AND CODE)

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    I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, w...

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    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

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    Build me an ALU using vhdl 4 days left
    VERIFIED

    Details will be provided upon in personal chat. Only experts apply, as I need product to be delivered asap.

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    SITUATION: I have a VHDL design for a custom processor + peripherals that needs to go into an FPGA. It passes functional simulation that uses VHDL testbenches. I am in the process of adding VHDL checkers. This design needs to pass timing simulation with a (soft) target frequency of 50 MHz, be programmed into an FPGA, and be verified using an off-the-shelf FPGA card. While I'm strong in digit...

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    Create Video tutorial of Verilog for students reference

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    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

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    mini arithmetic logic unit for signed and unsigned numbers

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    I have a Arduino sketch with Motor control. I want to change this code into VHDL or Verilog HDL. This is simple project. If anyone knows Arduino and FPGA, it takes one day to do it.

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    I have a VHDL+ TESTBENCH CODE. I want to create a small document. CODES AND MARKING SCHEME IS GIVEN THE DOC FILE.

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    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

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    Looking for a competent freelancer in FPGA, VHDL, Simulink and Python to do some work for me. Please read the attached document for full project specification

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    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

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    VHDL code of optimization algorithm fixing.

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    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

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    VHDL code of optimization algorithm fixing.

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    I need someone who knows verilog. I will provide the complete details in the chat.

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    I have been tasked to write a FSM in verilog. The details are in the attached file. I have also attached a previous code I wrote to change ASCII into 7 segment displays, as I know that will be helpful to completing the FSM.

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    clearly explain your datapath and control, and comment every single line of VHDL code

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    This is basically a VHDL Programming to implement ALU for two 4-bit input numbers. I need the vhdl program, constraint files and the schematic logic design as well. Please reply me asap as i need it by this Tuesday morning. Thanks

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    Hi, PLEASE HEIP. I have a activity. It is design a 4-bit asynchronous up down counter using xilinx software. I want truth table, k maps and VHDL CODE + TEST BENCH. Specially i want 2 different VHDL + TEST BENCH But all answers must be the same. IDE DESIGN SUITE 14.2V

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    I have to write the Verilog code(will post what i came up with below) for a 4-bit arithmetic/logic unit (ALU). The requirements are as follows: The ALU operate on inputs that are 4 bits wide. inputs aluin_a and aluin_b, a carry in named Cin and operation code named OPCODE. Inputs aluin_a, aluin_b and OPCODE are 4 bits wide. Cin is 1-bit wide. outputs will be alu_out and Cout. Output alu_out (wh...

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better. Link will be provided Please bid only if you can work with Quartus and V17.0 to be prpecise. Its needed ASAP

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    I want someone who can teach me system verilog and perl language completely . I need someone who can guide me to grab a opportunity as a design verification engineer.

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better. Link will be provided Please bid only if you can do. Its needed ASAP

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better Please bid only if you can do. Its needed ASAP

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language Please bid only if you can do. Its needed ASAP

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    I need help building ASIC using bitmain chips. I will need the PSU, hashing boards, controller designed. Delivarables would be vHDL or verilog files, BOM, PCB layouts, etc. that would be required in producing the ASIC machine by giving such delivarables to PCB manufacturer.

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    I need a MATLAB simmulink VDSL simulation to be completed. I am looking to see how distance will attenuate a VDSL signal. Can discuss more technical details.

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    To detect circles by hough transformation in verilog. the board is spartan-6.

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    This should include the Verilog HDL code of your MPZ design and simulation results to show the correct behavior, or any other interesting observation (e.g. maximum clock frequency of the design).

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    I've designed some verilog code, though it isn't working as expected- seemingly as I don't have enough experience with the terminology of the language. The code monitors a +12V/-12V Squarewave line. An external system drops the +12V portion of the Squarewave to 9V, then 6V, and then 3V- so that the line oscillates between 12/-12, then 9/-12, then 6/-12, then 3/-12 (all in volts). W...

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    We are looking for a talented and driven hands on Electrical Engineer who will be part of creating an incredible cutting edge technology system. And will focus on the design, construction, and troubleshooting of compact and reliable embedded electrical systems . This includes electrical sub-system design, integration, PCB layout, and frequent hands-on work in lab building and debugging electrical ...

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    I am using Altera DE2-115 FPGA board to configure it using Quartus software 17 lite edition. We have to use QSYS to assign addresses and link the processor, then assign inputs and outputs in VHDL and pin planner in Quartus, and then use NIOS II processor for Eclipse to write a program in C and run the board. I am seeking some help in building this mini thing. I am attaching a pdf file for the tas...

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    I need a verilog code that create a 16 bit "Calculator" that uses the slide switches as binary input, and uses the push-button cross as action triggers. The accumulator value should be displayed on the seven segment display in hexadecimal. the center button should be clear, and the four buttons should be ADD, SUBTRACT, AND and XOR.

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    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : fix neural network *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in training. *All of this should be printed in the ...

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    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

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    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

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    hello, I am looking for expert who build GL algorithm using VHDL. If you can do it, we will discuss in details.

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    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

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    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

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    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

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    BCD adder vhdl code which detects an overflow using vivado

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