Verilog vhdl jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    4,795 verilog vhdl jobs found, pricing in USD

    VHDL: Decode DCF77-Receiver signal and implement a stop watch along with.

    $193 (Avg Bid)
    $193 Avg Bid
    12 bids

    We wrote our verily code for simulation about a Bank Queue Project. We need improvement in our Implementation on BASYS

    $147 (Avg Bid)
    $147 Avg Bid
    11 bids

    implement 8-point FFT Architecture using verilog

    $40 (Avg Bid)
    $40 Avg Bid
    11 bids

    I have code, i want to correct one file and make according to my project file, which i am attaching.

    $40 (Avg Bid)
    $40 Avg Bid
    5 bids

    Verilog codes that fully compliant with EPC Gen2 Standard/ISO18000-6-C (RFID Tag baseband) including verification testbenches.

    $2057 (Avg Bid)
    $2057 Avg Bid
    5 bids

    it is described in the file below i need this done in an hour

    $61 (Avg Bid)
    $61 Avg Bid
    1 bids

    it is described in the file below i need this done in an hour

    $89 (Avg Bid)
    $89 Avg Bid
    9 bids

    Final outcome required : A system that takes images from a image sensor (OnSemi Python300) at 100FPS and stores them on a memory card and also runs Linux and is interactive through a touchscreen. As per my finding, it is best developed using ZYNQ. MAX10 FPGA with NIOSII is also a good choice. Current position: Avnet has made available the IP for interfacing the image sensor. So the bulk of work is done already. A designer is need who can take the IP and build the rest of the system. Relevant links will be shared during discussions. Since the most difficult part (the image sensor interfacing) is done already, this project shouldn't take much more than a week or so. Hence please quote your prices accordingly. Milestone payment preferred.

    $210 (Avg Bid)
    $210 Avg Bid
    3 bids

    I need some help to write a very simple code in VHDL. This work includes: combinacional circuits, state machine, gray code and flip flops.

    $15 (Avg Bid)
    $15 Avg Bid
    13 bids

    Verilog Morse Decoder Design  Input: Single input (only one bit(0-1))  Outputs: You should print at least one sentence(ASCII characters) to screen on Xilinx Environment. (Exp: 1 THE BEST ADVICE IS FOUND ON THE PILLOW)  Timing: Decoding a character should last at most 30 seconds. International Morse code is composed of five elemenets: X short mark, dot or ”dit” (.): ”dot duration” is one time unit long X longer mark, dash or ”dah” (-): ”dot duration” is three time units long X inter-element gap between dots and dashes within a character: one dot duration or one unit long X short gap (between letters): three time units long X medium gap (between words): seven time units long

    $51 (Avg Bid)
    $51 Avg Bid
    12 bids

    Hi I am looking for an expert who has in depth understanding of Tomasulo architecture for Processor , who can explain it to me in detail and also assign me a project in C/C++ or Verilog and work with me.

    $207 (Avg Bid)
    $207 Avg Bid
    5 bids

    Need a small technical work in very log and explanation. If you have free time today then u can bid here.

    $4 / hr (Avg Bid)
    $4 / hr Avg Bid
    20 bids

    writing algorithm in vhdl code with simulation

    $27 (Avg Bid)
    $27 Avg Bid
    14 bids

    Hi i need verilog expert who has cadence software. Bid here if you qualifies with the requirement. Thanks

    $5 / hr (Avg Bid)
    $5 / hr Avg Bid
    4 bids

    please check the details here .. My budget is 15$ and best review ============================================ if someone is efficient in php/mysql i have another task which neeed to be done online which is here in another link

    $16 (Avg Bid)
    $16 Avg Bid
    4 bids

    ...project:rn-- Summarize each step of your procedure in completing your project (e.g. What was the design process for your project?, What revisions to your design had to rnbe made?, What difficulties did you discover during verification/testing?, etc.)rno Provide enough detail that someone with a general understanding of your project's topic and the tools that you decided to use rn(e.g. VHDL, Xilinx Vivado, etc.) would be able to easily understand your rnproject.rn-- Explain your actual schedule of work and compare this to your proposed schedule of work (from your proposal). Explain any major deviations.rno For a research paper review:rn--Explain (in your own words) the most important points from the paper and for rneach point explain:rno Why is this p...

    $56 (Avg Bid)
    $56 Avg Bid
    7 bids

    Hi, This is a school's assignment. It it required to design a circuit that counts the number of ones in a 32-bit input X. The circuit has a 1-bit control input count, and a 6-bit output Y. The count input is connected to an internal controller that is used to control the counting process. As long as the count input is 0, the circuit is disabled, and the output is 0. Once the count input becomes 1, the input X is loaded into a 32-bit internal shift-register A, and the counting processes is executed. Beside I need to document the solution in a report that includes the following: 1. Problem definition. 2. At least two detailed alternative solutions. 3. Comparison of the alternative solutions. The comparison must be based on the complexity (the cost), and the scalability of the cir...

    $100 (Avg Bid)
    $100 Avg Bid
    1 bids
    $40 Avg Bid
    1 bids

    I have 4 tasks related to Digital logic design. I need help with them. Please bid if you know VHDL.

    $70 (Avg Bid)
    $70 Avg Bid
    21 bids

    I need to design a clock using 7 segment in verilog HDL language using Active HDL app see the pics i uploaded it might help to understand what im looking for requirements: - Verlog code - waveform

    $100 (Avg Bid)
    $100 Avg Bid
    3 bids

    rnfollowing blocks need to be implemented IN VHDL with their test bench - read_iq, demod, decimating FIR, Deemph, qarctan rnrnthe module should be synthesizable and implemented with FIFO rnrnwith following conditions -rnrnC macros should be implemented as inlined VHDL functionsrnUse the same quantization bit width as in the software.rnCreate a package with the array of filter coefficients and use generics to configure the filter taps and coefficients.rnHigh-level for-loops can be eliminated and replaced with streaming FIFOsrnUnroll internal function loops completely where applicable, such as shift registersrnApply one or more optimizations, such as loop unrolling or pipelining where applicablernImplement the division algorithm discussed in class for...

    $451 (Avg Bid)
    $451 Avg Bid
    3 bids

    to make a lowest common multiple design based on the c++ code given to me. Must also complete the ASM chart and datapath

    $138 (Avg Bid)
    $138 Avg Bid
    7 bids

    In this assignment, you will be building a streaming FM Stereo Radio. rnrnUsing the attached C software model, you will need to implement each of the function blocks in VHDL. Compile the software and run the input USRP data to see how the FM radio works. If you're on a Mac, you may need to adjust the header files and/or the soundcard interface. Use the "whereis" command to locate the headers. I recommend using visual studio to compare the inputs/outputs of each functional unit.rnrnIn your design, you should employ the following strategies:rnrnC macros should be implemented as inlined VHDL functionsrnUse the same quantization bit width as in the software.rnCreate a package with the array of filter coefficients and use generics to configure the...

    $39 / hr (Avg Bid)
    Urgent
    $39 / hr Avg Bid
    3 bids

    16x16 image to DCT store in a RAM/ROM and do IDCT to get back original 16x16 image.

    $12 / hr (Avg Bid)
    $12 / hr Avg Bid
    8 bids

    I need help in Analogue and Digital Electronics which involves vhdl as well. i will share details later. Thanks Its simple project. happy bidding..

    $6 / hr (Avg Bid)
    $6 / hr Avg Bid
    13 bids

    Hi, I am looking for someone with experience in verilog/VHDL programming or with Electronics background to modify some code. Details and files will be given in chat in what needs to be done in the code.

    $24 (Avg Bid)
    $24 Avg Bid
    5 bids

    The objective of this lab is to implement, in VHDL, an FSM+D single purpose processor that will evaluate the factorial of n. Copy the code and simulation image on a word document. The details of the project are in the attached word document

    $50 (Avg Bid)
    $50 Avg Bid
    1 bids

    The objective of this lab is to implement, in VHDL, an FSM+D single purpose processor that will evaluate the factorial of n. Copy the code and simulation image on a word document. The details of the project are in the attached word document

    $44 (Avg Bid)
    $44 Avg Bid
    1 bids

    Knowledge on MULTIPLEXERS, Concurrent behavioral VHDL description of a SN74F153, IEEE. Need to answer three questions.

    $22 (Avg Bid)
    $22 Avg Bid
    6 bids

    Assignment on VHDL design. I have Some problems . I think 12 problems and I need solutions to those problems and I can give u 2 days.

    $123 (Avg Bid)
    $123 Avg Bid
    24 bids

    Dear sir/maam, I have a job experience in VLSI design ,i am good in VHDL,VERILOG

    $15 (Avg Bid)
    $15 Avg Bid
    1 bids

    I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

    $105 (Avg Bid)
    $105 Avg Bid
    2 bids

    I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

    $81 (Avg Bid)
    $81 Avg Bid
    3 bids

    We need to Implement the MIPS-L single-cycle design using Verilog that can run the R-type (add, sub, and, or and slt), lw, sw, beq, addi, j, jr and jal instructions. Notice that the MIPS-L has a reset input. If reset = 0 then the MIPS-L will run as normal. If reset = 1, then the MIPS-L has its PC value set to 0. Your test bench should instantiate the MIPS-L module and the memory. It will also generate the clock signal and the reset. It will display the outputs “pc-out”, “alu-result”, and display the contents at certain memory locations.

    $158 (Avg Bid)
    Urgent
    $158 Avg Bid
    8 bids

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    $11 / hr (Avg Bid)
    $11 / hr Avg Bid
    2 bids

    I have some really old Verilog code that was generated from some obsolete hardware (~30 years old, specialized and no longer made). Unfortunately this recreation took into account numerous hops done for timing... so it's pretty messy. What I would like is for the Verilog code to be cleaned up without altering the gates (so equivalent logic, just removing the confusing hops). Typically you'll see lines like A<= B | C, B<=D, D<=E, E=F, F=G, G=H in the Verilog. So I'd like that simplified to just A<= H | C. I think their are programs that can do this, I just don't have access. The easiest way to work would be from the output backwards towards the inputs. I'd also like a circuit schematic as well, preferably in a format that is wi...

    $30 (Avg Bid)
    $30 Avg Bid
    4 bids

    Description: • Implement a 16-bit carry lookahed adder in Verilog that has 2-levels of carry lookahead. A functional (zero delay) should be used to verify circuit works properly and a nonzero simulation to evaluate performance. Structural(not behavioral) Verilog must be used. • Provided is a 16-bit ripple carry adder. Simulation and write-up: • Circuit diagram of 16-bit ripple carry adder and 16-bit carry lookahed adder • Critical path & delay of both adders under the unit gate delay model • Gate cost of both adders • Functional (zero delay) simulation results for both adders providing the Verilog implementation of your circuits work properly. Multiple data sets should be used to prove this. There should be ten data sets spannin...

    $34 (Avg Bid)
    $34 Avg Bid
    5 bids

    I need someone who will teach me verilog from scratch. Online teaching is preferred. I will prefer at least 20 classes. The classes must include explaining diffenent types of verilog code for ADL stuffs like sequential circuit, memory, combinational circuit with test bench as well. Interested candidates please contact me. Thanks in advance.

    $253 (Avg Bid)
    $253 Avg Bid
    14 bids

    I want to write verilog code as required my project pdf file. Please do it as it instructs the assignment pdf

    $150 (Avg Bid)
    $150 Avg Bid
    1 bids

    ...performance. Structural (not behavioral) Verilog must be used. Write up needs to be included which contains the following information: *circuit diagrams of both adders down to gate level *Critical path & delay of both adders under the unit gate delay model *Gate cost of both adders *Functional (zero delay) simulation results for the adders proving the Verilog implementation of your circuits work. Multiple data sets should be used to prove this. there should be ten data sets spanning all 16-bits of operands. *Analysis of the average delay across 5,000 randomly selected input patterns for both adders using the unit gate delay model. Specifically state how this average compares to the critical path delay. The files that need to be provided are the Veril...

    $66 (Avg Bid)
    $66 Avg Bid
    6 bids

    ECE 171 Fall 2015 Project 2 You are to design a combinational logic circuit to determine whether a given input i s a leap year . The year input consists of four BCD digits YO, YT, ...lose 30 points. Submit your project by upload ing a single zip file to D2L containing the following: • – your project report with all design work (diagrams, truth tables, K - maps) and timing diagrams • leapyear.v – your Verilog source code for the LeapYear module • iszero.v – your Verilog source code for the IsZero module • iszerotb.v – your Verilog source code for the IsZero testbench • divbyfour.v – your Verilog source code for the DivisibleByFour module • divbyfourt...

    $51 (Avg Bid)
    $51 Avg Bid
    3 bids

    I need a Verilog USART code to work in a Spartan 6 FPGA. The USART need be: Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte. The speed shod giving in a CLK input signal, the Data out should be a 10 Bits array (8 Data + Parity + Err detect). Should be similar to the Xilinx USART_RX KCPSM6 but with no buffers and with Parity + 1.5 Stop bits. The most important part are the noise filter, I have my own code already done for this and work 99% error free but I need 100% error free with noise then PLEASE DON'...

    $44 (Avg Bid)
    $44 Avg Bid
    5 bids

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    $24 / hr (Avg Bid)
    $24 / hr Avg Bid
    8 bids

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    $21 (Avg Bid)
    $21 Avg Bid
    5 bids

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    $11 / hr (Avg Bid)
    $11 / hr Avg Bid
    6 bids

    i need vhdl expert for my short vhdl project. details will be provided to suitable candidate

    $12 / hr (Avg Bid)
    $12 / hr Avg Bid
    5 bids

    adder register with 2 input (i.e. A, B), Clock, reset 32 bit adder register with 2 input (i.e. A, B), Clock, reset need to use Qurtus 2 (Altera ) software Write the Verilog code for a 32-bit Adder with registered inputs and outputs Write the Testbench code in Verilog and verify your design works as intended using VCS The inputs are: reset (active low), input1, input2, clock The output port is: result

    $14 (Avg Bid)
    $14 Avg Bid
    10 bids

    In this project we have to design the multi-cycle datapath for the modified MIPS-Lite (MML) ISA and we will model and verify your design using the Verilog Hardware Description Language (HDL).

    $177 (Avg Bid)
    $177 Avg Bid
    8 bids

    I have some codes and I need to complete it they are not long. everything is in the files

    $34 (Avg Bid)
    $34 Avg Bid
    7 bids