Verilog / VHDL jobs

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Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

240 jobs found, pricing in JMD

Edge detection by using laplacian 6 days left

I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

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Tcp sending on FPGA using verilog xgmii 6 days left

Tcp sending on FPGA using verilog xgmii xilinx vivado

Verilog / VHDL

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Sending and receiving tcpip xgmii packets over SFP+ 6 days left

This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

FPGA Verilog / VHDL

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plc program and hmi design Simulation 6 days left

I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL

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develop Simple SW to write on the IC Card/Server 6 days left

I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

C Programming Electronics Microcontroller PCB Layout Verilog / VHDL

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translate C++ code in systemc. 6 days left

translate c++ code in systemc and implement constrained random verification methodology.

C Programming C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)

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build a software 6 days left

translate c++ code in systemc. and implement constrained random varification methodology.

C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)

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Create a DLX Data Path Using VHDL 5 days left

Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

Assembly FPGA Microcontroller Software Architecture Verilog / VHDL

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build a software 5 days left

translate a C++ code in systemc module.

C Programming C++ Programming Verilog / VHDL

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convert the C++ language code in systemc. 5 days left

you have to translate C++ code in systemc language.

C Programming C++ Programming Software Architecture Verilog / VHDL

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Do VHDL project on the ModelSim 5 days left

I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

Electrical Engineering Electronics Engineering FPGA Verilog / VHDL

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verilog expert only 5 days left

more details will be given in the chat

Electrical Engineering Electronics Engineering FPGA Verilog / VHDL

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SoundLocator 5 days left

Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

Android Electronics FPGA Java Verilog / VHDL

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Project for Ajay N. 8 days left

Здравствуйте, anandori! Я обратил внимание на ваш профиль и хотел бы предложить вам свой проект. Мы можем обсудить детали в чате.

Android OCR PHP Python Verilog / VHDL

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Serializer & Desrializer Implementation using ZC706 and MTX 5 days left

Serializer & Desrializer Implementation using ZC706 and MTX

FPGA Verilog / VHDL

$3620 / hr (Avg Bid)

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OpenCL FPGA Code modification 4 days left

I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

C Programming Cryptography FPGA OpenCL Verilog / VHDL

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Circuit at logism 4 days left

implement a digital circuit in Logisim for a door lock.

Circuit Design Electrical Engineering Electronics Microcontroller Verilog / VHDL

$3120 (Avg Bid)

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expert in vivado vhdl needed 4 days left

expert in vivado and vhdl needed asap

Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL

$3142 (Avg Bid)

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digital logic design circuit in logisim 4 days left

there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do.

Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL

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digital circuit in logisim 4 days left

we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b)

Circuit Design Electrical Engineering Electronics Microcontroller Verilog / VHDL

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