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vhdl

€18-36 EUR / hour

Closed
Posted over 7 years ago

€18-36 EUR / hour

Project ID: 12029507

About the project

13 proposals
Remote project
Active 7 yrs ago

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13 freelancers are bidding on average €25 EUR/hour for this job
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Dear sir I have more than 9 years experience in digital design using vhdl, please check my profile
€27 EUR in 3 days
4.9 (444 reviews)
7.9
7.9
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Hello! Please look at my profile! I have 6 years experience wit vhdl design! I can help you right away! I am here! Please send me a message with all the detailed requirements of your board! Have a great day!
€20 EUR in 24 days
5.0 (46 reviews)
5.8
5.8
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Hi I have vast experience in Xilinx suite and vhdl/verilog programming. Please contact me to discuss the project details.
€22 EUR in 10 days
5.0 (26 reviews)
5.0
5.0
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Hello, I understood the initial scope of this project. Although i want to discuss further this job in order to prepare the final concept for this project. After Complete discussion over the call or in chat, i will prepare following things for you - Technical Project Proposal - Flow chart for this Project - Execution plan (Step by step procedure with explanation how and at what that we are going to execute a particular task)
€30 EUR in 10 days
5.0 (3 reviews)
4.3
4.3
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A proposal has not yet been provided
€30 EUR in 10 days
4.6 (15 reviews)
4.2
4.2
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Hi, I am an electronics engineer having experience of FPGA/VHDL based digital system design for more than 5 years.
€18 EUR in 10 days
5.0 (9 reviews)
3.4
3.4
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I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus 13.0sp1, EDK embedded tools & worked on Virtex-6 ML605, Virtex-5 LX110T, Virtex-4 ML401 , Spartan6, Spartan 3E, SOC Znyq Zedboard and MicroZed boards. I have completed 1G data traffic project where in-depth IEEE Ethernet 802.3 packet parsing is done according to rule set defined for voice & data packets. Each TCP, UDP and SIP packet is processing and transmits to destination and vice versa at receiving end. Xilinx Ethernet core is used only for capturing of packet from FPGA. The clock frequency here is 125Mhz for each I have also completed 10G data traffic project where software part is implemented using Microblaze to configure NELOGIC chip via MDIO protocol & send real time results of 200 registers to PC via uart protocol. I have debugging experinece between PMA and PCS layers. The custom IP is configured in mixed Vhdl / verilog to handle 10G data Traffic. I have also acquired Xilinx trainings such as Advanced Features & Techniques of Embedded Systems Development, Debugging Tecniques Using ChipScope Pro Tools from So-Logic Vienna. Please share the project detail. I can work online if it is suitable for you. I am free can start work immediately and can work upto 60 hrs per week. Further we can discuss
€18 EUR in 60 days
5.0 (4 reviews)
3.4
3.4
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Hi John here, I am really interested to work on this project, I can start the work now , and can provide the best services from my end. Please come on chat to discuss more about the project. Thanks!
€30 EUR in 10 days
0.0 (0 reviews)
0.0
0.0
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Hello, We are a team of embedded hardware and software professionals with experience in vhdl coding and simulation Would like to know more details about the project. Looking forward to work on this project. Please feel free to contact us for any further discussions. Thanks and Regards EmWorld
€25 EUR in 20 days
0.0 (0 reviews)
0.0
0.0
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My name is Maciej Gasienica and I represent company JPEmbedded. Since 2006 JPEmbedded provides comprehensive embedded systems design and implementation services. Most of our customers are west European manufacturers representing industrial automation, automotive, medical and energy markets. Currently our team consists of 26 engineers. I noticed that your 'vhdl' project fits perfectly with our experience, thus I would like to offer our services. In order to confirm our experience in requested area I'm sending the examples of the projects we completed: * Encryption device - the task was to design the device consisting of ARM micro-controller and FPGA, which encrypts and decrypts 1 GBit Ethernet communication in real time. JPEmbeddded implemented in VHDL language, FPGA firmware for online encryption or decryption of Ethernet frames on Xilinx FPGA using proprietary protocol. Beside this, firmware for ARM micro-controler was developed. * Mipi TraceBox device (Intel Atom, Virtex 5 FPGA, Android), * Image processing (FPGA and DSP platforms) - FishEye image corrections (endoscope), MatrixMM, 4q, moving objects discovery... * Firmware for electroenergetic circuit protection systems (C), More examples, detailed information about our company and reference letters available upon request. Availability: december 2016 (to be confirmed). yours faithfully, Maciej Gasienica JPEmbedded
€34 EUR in 40 days
0.0 (0 reviews)
0.0
0.0

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Germany
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Member since Nov 9, 2016

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