We need to Implement the MIPS-L single-cycle design using Verilog that can run the R-type (add, sub, and,
or and slt), lw, sw, beq, addi, j, jr and jal instructions. Notice that the MIPS-L has a reset input. If
reset = 0 then the MIPS-L will run as normal. If reset = 1, then the MIPS-L
has its PC value set
to 0. Your test bench should instantiate the MIPS-L module and the memory. It will also generate
the clock signal and the reset. It will display the outputs “pc-out”, “alu-result”, and display the
contents at certain memory locations.
Dear sir
I have seen the attachment and I can do it perfectly I have more than 8 years experience in digital design using verilog and vhdl please check my profile also please message me so that we can discuss
Hey, I am an engineering student and I've experience working with Mips systems because my college teach us a lot of thing using that architecture.
You can check my profile, I just finished your job but implemented on C, I know I can do your job.
Please contact me if you have any questions, I'm here and I can gladly answer any doubts you have.
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Hi
Verilog based system design is my main area of work; and Computer Architecture is my specilization [I have a masters in Computer Architecture].
I have seen the instruction set that you want to implement. Let me know if you need my services
Best Regards
Syfar
Hi
We are experts in Verilog/VHDL RTL coding. We have the codings readily available in our previous project just need to tweak the instruction set as per your requirement.
Ping us once your online we should be able to deliver it in couple of days.
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Thanks and Regards
DVIGurus