Computer Science—Verilog, VHDL

I am looking for a VHDL expert: Basically everything needs to be mapped to [login to view URL] (attached). A new file needs to be created called [login to view URL], which includes [login to view URL] (to be manipulated accordingly or port mapped with the counter requirements noted in the diagram), and [login to view URL] (to be created). So [login to view URL] will include the counter and the ram. [login to view URL] will include 3 counters: Counter A - read/write Counter B - Adder Counter C - Test Data *Have Do Writes for 5 Cycles and Read for 5 Cycles Please let me know if this helps. I've attached the .vhd files to be used for [login to view URL] and tb_counter.vhd. One more thing; I do have suggested code to start with for RAM from my instructor. Of course it will have to be changed in order to work with the "memchip". Please let me know if I can answer any questions. thanks. LIBRARY ieee; USE [login to view URL]; ENTITY ram is GENERIC ( bits: INTEGER := 8 -- # of bits per word words: INTEGER := 8 ); -- # of words in the memory PORT ( wr_ena : IN STD_LOGIC; -- write enable clk : IN STD_LOGIC; -- clock addr : IN INTEGER RANGE 0 to words -1; data_in: : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)); END ram ARCHITECTURE ram of ram IS TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0); signal memory: vector_array; BEGIN PROCESS (clk, wr_ena) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (wr_ena = '1') THEN memory(addr) <= data_in; END IF; END IF; END PROCESS; data_out <= memory(addr); END ram;