1ns Bin Size Histogrammer, FPGA + ADC

$750-1500 USD

Closed

Posted

almost 5 years ago

$750-1500 USD

Paid on delivery

I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edges at t=3.2ns, 28.5ns, 528.6ns and 1528.7ns. Then in the histogram, Bin #25, Bin #500 and Bin #1000 have 1 respectively, and all other bins have 0s. SPEC: Bin Size: <=1ns # of Bins: Up to 10K What I need from you: 1. A plan on what I need to buy to build this system. I have a ZCU102 board. So maybe something like AD9234-LF1000EBZ? Do let me know your plan in your proposal. 2. The deliverable is the firmware, including ZCU102 PL side RTL and bit file, Petalinux Image and drivers. 3. Remote support, to set up the whole system. 4. A block diagram and a brief explanation about your RTL code. Verilog is preferred. Please in the proposal, let me know how long would the project take and how much would you ask to build it.

Electrical Engineering

Electronics

FPGA

Verilog / VHDL

Project ID: 19314823

About the project

1 proposal

Remote project

Active 5 yrs ago

Looking to make some money?

Email address

Benefits of bidding on Freelancer

Set your budget and timeframe

Get paid for your work

Outline your proposal

It's free to sign up and bid on jobs

1 freelancer is bidding on average $1,250 USD for this job

@fjot

I think that the pulse delay measurement can be done without any external components. If your information about the pulses input level (0V - 1.1V) is correct, then LVCMOS12 (1.2V IO standard) could work with this. If the input signaling would be on the edge it would be possible to clean up the signal and convert to e.g. LVDS with an external high-speed comparator component. Xilinx UltraScale+ HP IO works up to 1250Mbit/s e.g. in case of RX SERDES. In case we run this with exactly 1000Mbit/s rate we could measure the pulses with +/-0.5ns accuracy. Still, from start to end measurement this probably results in +/-1ns ambiguity. Even Zynq Ultrascale is not needed, Zynq 7000 would do the job. Here I make this proposal to implement the pulse delay measurement using ISERDES approach: LVCMOS12 input -> ISERDES -> delay measurement -> RAM-based histogram The module would have AXI interface to the PS domain. My proposal is that I could implement the RTL and prove the operation using simulation, but I can't test it on HW and I cannot integrate it with SW/Linux.

$1,250 USD in 5 days