Completed

system verilog alarm clock and DE10-lite FPGA programming

All code written in system verilog and the functions mod or divide not allowed

Time should be displayed on the 6 digits of the seven segment displays (HHMMSS)

-hours displayed in military time

-when SW2=1, alarm is set and 6 digits display alarm time

-when KEY0=0, the alarm is reset to 0, KEY0 takes priority over SW2

The alarm clock must be accurate, divide down the 50MHz clock at PIN_P11 as necessary on the DE10-Lite. For all frequeny dividers use a 50% duty cycle. This should be constructed similar to a counter.

Switch functions:

SW0=1 =reset

SW1=1 =time set

SW2=1 = alarm set

SW3=1=set hours SW3=0=set minutes

SW4=1 run clock time

SW5=1 run active alarm

KEY0 pressed (=0) causes alarm reset

KEY1 pressed (=0) sets whatever is selected at 2 Hz clock rate

The simulation verifiaction module should be:

module alarm_clock(input CLK_2Hz, reset, time_set, alarm_set, sethrs1min0, run_clock, activatealarm, alarmreset, runset, output logic [7:0] sec, min, hrs, min_alarm, hrs_alarm, output logic alarm);

write code for a test bench to do the following:

-do a reset

-set alarm to 5 hours 30 minutes

-set time to 5 hours 29 minutes

-activate alarm

-activate run time

-after alarm goes off, reset

-reset clock

write code for physical verification/programming of DE10-Lite

module alarm_clock_pv(input CLK, SW5, SW4, SW3, SW2, SW1, SW0, KEY1, KEY0, output logic [6:0] SEC_LSB, SEC_MSB, MIN_LSB, MIN_MSB, HR_LSB, HR_MSB, output logic LED7, LED5, LED3, LED2, LED1, LED0);

(module should instantiate alarm_clock module)

The clock is associated with a 50MHz clock on FPGA PIN_11, and will have to be divided down to 2Hz using a frequency divider at 50% duty cycle

LED functions: LEDs 0-5 turn on when corresponding switches turn on, LED7 is the alarm and should blink at a 2Hz rate until reset

Button Functions: KEY0 clears alarm, KEY1 gives hours or minutes to set, depending on SW3

-only set hours and minutes so seconds should be clear when setting alarm, whenever alarm set switch is activated alarm time should be shown, default is time

Seven Segment Display: write code to transform from numbers to arrays to the 7 segment displays. Will need to break numbers up into high order and low order digits and transferring them to the seven segment displays.

Skills: FPGA, Microcontroller, Verilog / VHDL

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Project ID: #22154312

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ducdctoandh

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ahmedmohamed85

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Fpgageek

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