Mohamed M. Profile

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$30 USD / hour

alexandria,

egypt

$30 USD / hour

It's currently 12:53 PM here

Joined December 7, 2022

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Mohamed M.

@Majiidd

0.0

(0 reviews)

0.0

100%

$30 USD / hour

alexandria,

egypt

$30 USD / hour

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Verilog/SV/VHDL RTL coding | FPGA | ASIC | VLSI

Experienced Digital IC Design Engineer and RTL Coding Expert, offering FPGA/ASIC RTL Coding in Verilog, SystemVerilog, and VHDL, with Multilingual Tutoring. Available Round-the-Clock | Flexible Pricing | Prioritizing Service Excellence My Experience: I've worked extensively with FPGAs, utilizing various FPGA boards such as MAX Family, DE-series, Cyclone V, ZYNQ, PYNQ, Basys3, Artix7, and Efinix T120. I'm well-versed in Vivado, Vitis HLS, Quartus, and Efinity for FPGA design. For ASIC design, I've harnessed the power of Synopsys tools, employing both TCL scripts and GUI. I'm proficient in DesignCompiler, Formality, and DFT. I am also proficient in documenting designs using three methods: LaTeX, Microsoft Word, and Markdown language. My portfolio showcases a diverse array of complex designs across fields like image processing, cryptography, communication protocols, and processors, all implemented using HDLs. Let's collaborate and bring your project to life. Reach out to discuss the details, and I'll be here to assist you at any time. Your success is my priority. Key Skills: - Digital IC design - RTL Coding using Verilog/SystemVerilog and VHDL - Simulation and debugging using QuestaSim/ModelSim - STA and CDC - FPGA/ASIC flow - Communication protocols such as: UART - SPI - I2C - AXI - Programming languages such as: Python • C/C++. - Knowledge in scripting Language : TCL. - Documentation languages such as: Markdown • Latex. Tools: Vivado IDE • Quartus prime • Efinity IDE • VS Code • Xilinx ISE • ModelSim/QuestaSim • Synopsys Deesign Compiler •MATLAB • Git/GitHub • Notepad++.

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Portfolio

An RTL modeling for a wash machine controller, using Verilog HDL.

-Designed a controller for a washing machine that has the following states:

--IDLE
--FILLING WATER
--WASHING
--RINSING
--SPINNING

-also supports the following:

-A double wash option.
-A timer pause during the spinning phase.
-Multiple operating frequencies.
-An asynchronous active low reset.

For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/Washing-Machine

Washing Machine Controller, using Verilog HDL.

Summary
UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a communication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit and receive serial data. In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form and transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the transmitting UART's Tx pin to the receiving UART's Rx pin.

For more detailed information visit my GitHub: https://github.com/MuhammadMajiid/UART

Full UART implementation using Verilog HDL

Implementation of 32-bit Single-Cycle MIPS processor based on Harvard architecture, MIPS processor is from the RISC family, It supports 3 different types of instructions such as: R-Type, I-type, and J-type. It is supported with a CLA Adder -Carry Look Ahead Adder- for fast computations. The architecture relies on 3 main components:

-Control Unit.
-Data Path.
-Data/Instruction Memory.

For detailed information visit my GitHub: https://github.com/MuhammadMajiid/MIPS-Processor

Implementation of 32-bit MIPS-processor using SystemVerilog

Implementation of the 128-bit AES protocol is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001. AES is widely used today as it is a much stronger than DES and triple DES despite being harder to implement.

-Points to remember:

--AES is a block cipher.
--The key size can be 128/192/256 bits.
--Encrypts data in blocks of 128 bits each.

That means it takes 128 bits as input and outputs 128 bits of encrypted cipher text as output. AES relies on substitution-permutation network principle, which means it is performed using a series of linked operations involving replacing and shuffling the input data.

-Working of the cipher :
AES performs operations on bytes of data rather than in bits. Since the block size is 128 bits, the cipher processes 128 bits (or 16 bytes) of the input data at a time.

for more information visit my GitHub: https://github.com/MuhammadMajiid/AES

Advanced Encryption Standard (AES) modelling, using Verilog

Washing Machine Controller, using Verilog HDL.

Full UART implementation using Verilog HDL

Implementation of 32-bit MIPS-processor using SystemVerilog

Advanced Encryption Standard (AES) modelling, using Verilog

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Experience

IEEE SSCS Alex SC

Mar 2022 - Present

◦ Efficient Synthesizable RTL coding: using Verilog/SystemVerilog HDLs ◦ Computer Architecture: Undersatnding of the under-hood of the computer by studying the MIPS processor architecture and designing it by SystemVerilog HDL. ◦ Verification: Understanding of the basic concepts of verification using SystemVerilog HDL.

NajahNow

Aug 2022 - Nov 2022 (3 months, 1 day)

◦ Efficient Synthesizable RTL coding: using Verilog HDL, Self-test test benches. ◦ Synthesis and implementation: used Xilinx ISE to implement the design on Spartan-6, I/O planning layout using the PlanAhead tool, tested the design with multiple clock domains and applied to time constraints. ◦ Acceleration FPGA Design: used Vivado IDE to implement the design on the Zynq-7000 board, used the logic analyzer to debug the design and created IP then used the IP integrator to create a block design.

Education

Bachelor degree of Electronics and Electrical Communication Engineering

Alexandria University,

Egypt

2019 - 2023

(4 years)

Qualifications

NajahNow, One Lab, Zewail City

2022

- Efficient Synthesizable RTL coding: using Verilog HDL, verified by Self-test test-benches. - HDL Synthesis and implementation on FPGA: used Xilinx ISE to implement the design on Spartan-6 FPGA, I/O planning layout for pin assignment using PlanAhead tool, tested the design with multiple clock domains, and applied timing constraints. - Acceleration FPGA Design: used Vivado IDE to implement the design on the Zynq-7000 board.