Grain Cipher using VHDL
This picture shows the RTL view of a Grain cipher using Synplify pro software, the design was developed using VHDL, also a test bench was created using VHDL to verify the operation of the Grain Cipher
About Me
10 year's experience in digital system design using VHDL and verilog for FPGA's and CPLD's both for Xilinx and Altera Chips. I also have 10 years experience in working with Xilinx Ise form version 6.2 to 14.7 and Altera Quarus 2 for VHDL , verilog, system verilog and ip in addition to experience in Vivado design tool, and HLS and digital design using zynq7000
