vpradeep83

Looking to work as a freelancer on ASIC Digital Verification and Design projects. Career Summary SoC Verification ----------------------- - System Verilog/OVM based verification environment - C Based verification environment - Reference Verification Methodology based self checking Test Bench design - Synthesizable Test Bench design - Behavioral Models, Bus Functional Models using Verilog HDL - Data comparisons, Configuring Test Bench using PERL scripting - Assertion Based Verification using System Verilog Reusable IP Design ----------------------------- Modular Design of the IP Block, with separated Bus Interfaces and Core Functionality to support Design Reuse State Machine Design Handling Clock Domain Crossing Synthesizable RTL coding using Verilog HDL Fundamentals in ASIC, FPGA Synthesis Synthesized simple modules for ASIC, FPGA