You need to develop an architecture simulator for the MIPS computer whose organization is shown in Figure 1

To experience the design issues of advanced computer architectures through the design of an analyzer for a

simplified MIPS CPU using high level programming languages. The considered MIPS CPU adopts the

CDC 6600 scoreboard scheme to dynamically schedule instruction execution and employ caches in order to

expedite memory access.

Project Statement::

Consider a simplified version of the MIPS instruction set architecture shown below in Table 1 and whose

formats are provided at the end of this document.

You need to develop an architecture

simulator for the MIPS computer whose

organization is shown in Figure 1. The

simulator is to accept as an input a

program in the MIPS assembly using the

subset of instructions in Table 1. The

output of simulator will be a file

containing the cycle time at which each

instruction completes the various stages,

and statistics for cache access.

Below attached file contains Table 1 and figure1

C Programming Java Python

Project ID: #28269886

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