design a 8 bit processor with the following specifications
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Design a 8 bit processor with the following specifications1:
1. The processor has seven 8-bit registers A, B, C, D, E, H and L.
2. The processor begins by executing instruction at address 0.
3. It connects with an external memory containing 32 8-bit words. The memory has a
tristate output with active low signals rd and wr.
4. It has instructions MOV, MVI, LDA, STA, ADD, SUB NOP and HLT. It can also add
or subtract data directly from memory.
5. The op-codes for the instructions are defined as follows. The registers A, B, C, D, H
and L are coded as 111, 000, 001, 010, 011, 100 and 101 respectively. The letter M
always refers to the contents of the memory address in the least significant 5 bits of
the L register2. The opcodes may then be described as follows:
01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0)
01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory)
01 d2d1d0 110 : MOV r, M (copy memory contents to register d2d1d0)
01 110 110 : HLT (halt the processor)
10 000 s2s1s0 : ADD r (add reg s2s1s0 to register A)
10 000 110 : ADD M (add memory contents to register A)
10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A)
10 010 110 : SUB M (subtract memory contents from register A)
11 1a4a3 a2a1a0 : STA addr (store A to memory address a4a3a2a1a0)
00 1a4a3 a2a1a0 : LDA addr (load A from address a4a3a2a1a0)
00 d2d1d0 110 : MVI r, dd (copy the word in the next memory
address to register d2d1d0)
00 000 000 : NOP (do not do anything)
Test the processor by loading the following code to your memory. (Copy the data to a
file and read it to the memory using $memreadh).
35 47 80 0E 05 91 2E 18 66 6F 74 3E 01 00 86 00
2E 14 96 76 14 1E 00 00 15 00 00 00 00 00 00 00
(See the next page to see the action of this program)
1The architecture specifications and the instruction set/codes is (to a great extent) a subset of the Intel
8085 processor
2in 8085, M refers to contents of memory location pointed to by the 16 bits in H-L.
Digital Systems 2
This program code can be interpreted as follows:
Memory contents
addr. data meaning action
(hex)
0 35 LDA 21 A <-- 30
1 47 MOV B,A B <-- 30
2 80 ADD B A <-- 60
3 0E MVI C,5 C <-- 5
4 05
5 91 SUB C A <-- 55
6 2E MVI L,24 L <-- 24
7 18
8 66 MOV H,M H <-- 21
9 6F MOV L,A L <-- 55
10 74 MOV M,H mem[23] <-- 21
11 3E MVI A,1 A <-- 1
12 01
13 00 NOP
14 86 ADD M A <-- 22
15 00 NOP
16 2E MVI L,20 L <-- 20
17 14
18 96 SUB M A <-- 2
19 76 HLT
20 14 DB 20,30,0,0,21
21 1E
22 00
23 00
24 15
Please give the following answers:
• Design approach
• The complete design including datapath sketch and control description.
• Verilog code of the processor, memory and a properly set-up test bench (including
good comments)
• Simulation waveforms of your system showing contents of PC, IR and the registers,
Project ID: #2566619
About the project
10 freelancers are bidding on average $297 for this job
Dear sir, I have more than 5 years experience in digital design using FPGA best regards;
Hi, I can do this for you HIGH QUALITY guaranteed. I have been part of several PROCESSOR DESIGN projects... More info on PM..
Hello! I can deliver you custom code, for the required specifications. I can do it either VHDL or Verilog (as you prefer). I will also provide a test environment to demonstrate the functionality of the code. Rega More
Electronic engineer with MS and more than 5 years experience in FPGA. Ready to help you.
I have done similar work during my MS thesis so I can do it. If employer needs more clarification then he can contact me . I can provide the block diagram of my work. My processor was infact 32 bit processor.
Hi Dear, I have studied all the specifications mentioned by you and I am interested in your project. I have completed one such project exactly similar in which I designed Single cycle and multicycle processor with 3 More
