build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit should be a functional waveform for verification. It is also mandatory that any four units be connected together or working together using only Verilog HDL, then that design can be placed as a symbol on a schematic diagram. Use Quartus to build your project. Your design need to also be verified on the DE2-115 FPGA Altera board.
Dear sir
I have more than 10 years experience in digital design using Verilog, also i already have the Altera DE2-115 board, i would be happy to do this project for you
Best regards
Relevant Skills and Experience
Verilog, Quartus, DE2-115
Proposed Milestones
$166 USD - after delivary
Additional Services Offered
$1 USD - online assistance
when do u need it finished?
Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you!
Relevant Skills and Experience
Verilog and Digital Design - 4+ years
CPU Design - 2+ years
Proposed Milestones
$50 USD - Initial design details
$105 USD - Final design
Have working knowledge on hardware engineering specifically in VHDL and FPGA. Also, expert in computer architecture and will definitely be able to deliver on time and within your specification.
Relevant Skills and Experience
Using SignalTap and Quartus II, Cyclone device, debugging, board bringup verilog and system verilog.
Proposed Milestones
$44 USD - Understanding project requirements and dateline
$20 USD - Checkpoint for work delivery
$80 USD - Delivery of project
Additional Services Offered
$200 USD - Available on support after project delivery or any other enhancements