finite state machine synthesis

Dear sir I have more than 10 years experience in digital design using vhdl please check my profile also please message me so that we can discuss

I have red the description you provided. As part of this offer I will design a state machine(as a diagram)/implement it in VHDL/simulate and finally synthesize the design and capture block diagram. for both traffic li More

Hello, I am an electronics engineer having experience in VHDL based system design for more than 5 years.

A proposal has not yet been provided

Hey I am an electrical engineer and have done several projects using xilinx ise with vhdl. I already have a few working modules for this project. so please ping me up with more details so that we can get this done asap More

- i have a strong background in verilog and fsm design . - i am the lowest price you can get . - i know how to deal with questa / xilinix .

it’s a typical FSM style circuit. i've drew a transition diagram RIGHT NOW. please feel free to contact to me.