In my current role as an RTL Design Engineer, I have gained extensive experience in Verilog language and have actively engaged in configuring and integrating the Cortex-M33 with SOC, as well as RTL Design for Debouncer. Additionally, I have been involved in Synthesis and Implementation, where my duties entail identifying and troubleshooting errors, and subsequently creating constraints to address these issues. To achieve this, I utilize tools such as Synplify and Vivado for design synthesis. My responsibilities cover the entire front-end design process, including RTL design, synthesis, and implementation.