single-cycle MIPS processor

A FPGA/IC design expert with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design.

Hey! Please check my reviews and profile to know more about me and my work. It would be great if I could help you out.

I already designed Pipeline 5 stages on Verilog MIPS coding. I can share with you same project just updating some more modification according to you demand. Come on chat for more discussions… Thanks. waqas

I have basic knowledge in Verilog but I have ready your single cycle MIPS processor because of a past task in my school. I can deliver it to you and explain in it perfectly within 2 hours after you choose me.

I took verilog/fgpa lessons in my 2nd year of school. I am familiar with it. I did traffic light simulator before and I believe I can deal with your homework too