An Improved Dynamically Reconfigurable Pipelined Adaptive Viterbi Decoder for High Throughput

$250-750 USD

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over 8 years ago

$250-750 USD

Paid on delivery

An Improved Dynamically Reconfigurable Pipelined Adaptive Viterbi Decoder for High Throughput wirless communication

Verilog / VHDL

Project ID: 9111305

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5 proposals

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5 freelancers are bidding on average $511 USD for this job

@raulbehl

A proposal has not yet been provided

$750 USD in 14 days

5.0

(79 reviews)

6.2

@punamsengupta

A proposal has not yet been provided

$277 USD in 10 days

4.8

(13 reviews)

3.8

@sujithkuroor

A proposal has not yet been provided

$500 USD in 1 day

5.0

(4 reviews)

0.3

@parikshitsaha001

I am having knowledge on fpga implementation of different algorithms & recently working on vhdl based image processing implementation.

$577 USD in 10 days

0.0

(0 reviews)

0.0

@shenjie93

I'm experienced in FPGA development particularly in Verilog. I also have a Altera DE1 SoC board so I can make sure the synthesized code works on your part. I want to help you and please let me know as soon as possible so that I can start early.

$450 USD in 10 days

0.0

(0 reviews)

1.0

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About the client

Egypt

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Member since Dec 12, 2015

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An Improved Dynamically Reconfigurable Pipelined Adaptive Viterbi Decoder for High Throughput

$250-750 USD

$250-750 USD

About the project

Looking to make some money?

Benefits of bidding on Freelancer

About the client

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