Migration of Verilog Testbenches to UVM

Hi I am interested in your project I am an expert in Verilog with experience working in pre-silicon validation building tb in UVM/OVM environments and performing random constraint testing We can discuss the compensation and the due date

Hello, I am working in the ASIC design flow for 10 years. I have experience in RTL design, and used VCS FOR SIMULATION with VMM/UVM verification environment, DC for synthesis and ICC for layout. Please contact me.

I am a trained Engineer in Design and verification using verilog,systemverilog and UVM,I can handle these UVM architecture verification scheme.I have an experience of 4 years in VLSI field.

7 years of industrial experience of FPGA and ASIC development and verification experience. Can quickly update your system verilog tb into uvm tb.

Dear Sir or Madam, I hope my proposal finds you well. Please accept my proposal for your attractive project. I have three years experience on UVM Verification Project of DO-254 compliant avionics FPGA projects. Considering the fact that avionics projects are sensitive and DO-254 standards requires fully verification of the designs, has made me to use all features of UVM Methodology. For more information, please contact me via email and looking forward to hear from you. Best Regards, Ardi Jorganxhi

Hi, My name is Anjana B. I am a trained VLSI front-end engineer with good hands-on experience in Verilog, System-Verilog and UVM. I think my skillsets match your requirements. Looking forward to getting conected. Regards Anjana B

I have working Experience of 1.5 years as an ASIC Verification Engineer and Developed many UVM testbenches from scratch. I am proficient in System Verilog, C, C++ and UVM and worked on IP as well as SoC Verification Team. This task will be easy for me.