I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus 13.0sp1, EDK embedded tools & worked on Virtex-6 ML605, Virtex-5 LX110T, Virtex-4 ML401 , Spartan6, Spartan 3E, SOC Znyq Zedboard and MicroZed boards.
I have completed 1G data traffic project where in-depth IEEE Ethernet 802.3 packet parsing is done according to rule set defined for voice & data packets. Each TCP, UDP and SIP packet is processing and transmits to destination and vice versa at receiving end. Xilinx Ethernet core is used only for capturing of packet from FPGA. The clock frequency here is 125Mhz for each sample.
Please share the project detail. I can work online if it is suitable for you.
I am free can start work immediately and can work upto 60 hrs per week. Further we can discuss it and I look forward to receiving your response.
Regard
Mahar