Verification of bus interconnecting

$30-250 USD

Closed

Posted

over 2 years ago

$30-250 USD

Paid on delivery

Project is about verification of Bus interconnect using UVM. The bus interface are AHB and APB based.

Verilog / VHDL

Project ID: 31942473

About the project

4 proposals

Remote project

Active 2 yrs ago

Looking to make some money?

Email address

Benefits of bidding on Freelancer

Set your budget and timeframe

Get paid for your work

Outline your proposal

It's free to sign up and bid on jobs

4 freelancers are bidding on average $218 USD for this job

@liveexperts123

Hi there, I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the project. Thanks. ,.

$250 USD in 6 days

4.8

(5 reviews)

5.5

@kickerslevi

MASTERS IN ELECTRICAL ENGINEERING GOOD IN VERILOG HELLO DEAR CLIENT I have gone through your project details and the work is DOABLE since its within my area of EXPERTISE.I will tackle are required guideline to deliver desired goal Please consider my bid. THANKS`+

$200 USD in 3 days

0.0

(0 reviews)

0.0

@Ehtsham009

I'm a professional design verification engineer with broad experience of UVM based verification. I have worked with APB and AHB protocol in multiple projects so I can best do your job. Please contact me for further requirements discussion.

$222 USD in 7 days

0.0

(0 reviews)

0.0

@oguzsanli

I have been working for 3 years in lots of UVM project in a technology company. I have worked about I2C,UART,SPI,Ethernet 10/100/100mbps,AXI-Lite,AXI-Stream,CAN,CAN FD,TileLink. I can help you about this project.

$200 USD in 7 days