SystemVerilog and UVM.

₹600-1500 INR

Closed

Posted

over 3 years ago

₹600-1500 INR

Paid on delivery

Can anyone teach me SystemVerilog and UVM (in 2 months) with projects?

Very-large-scale integration (VLSI)

Verilog / VHDL

FPGA

Project ID: 27828826

About the project

4 proposals

Remote project

Active 3 yrs ago

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4 freelancers are bidding on average ₹8,056 INR for this job

@raulbehl

Hey! Please check my reviews and profile to know more about me and my work. It’d be great if I could help you out!

₹11,111 INR in 30 days

4.9

(77 reviews)

6.1

@moaazkh96

hi, I am a senior digital design engineer, I have a wide knowledge in digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE and Quartise. I am an online tutor in digital design and system verilog and I can help you Please contact me to know more about your needs. Regards, moaaz.

₹5,000 INR in 7 days

4.9

(6 reviews)

3.3

@suryanil

Experienced Verification Engineer with 6years of experience. Expertised in SV and UVM. Please contact me to discuss details of my teaching plan along with projects.

₹11,111 INR in 30 days

0.0

(0 reviews)

0.0

@amit20112011

Hi, I have 8+ year of experience in system Verilog and UVM. I will teach you the basics with clear concepts and simple examples. You can take one demo first and then you can decide. Thanks, Amit

₹5,000 INR in 30 days