I need to write a TCL script (synopsys tool) to cut and remove overlaps from a given circuit design. Given Vss - ground and Vnnaon - power, the objective is to remove parts of Vss that are overlapping with Vnnaon.
i have this partial working script, but it fails for some cases of multiple overlaps
I've developed several TCL scripts, down from simple string appending all the way up to manipulating reporting files.
So, reach me via chat to see if I can help u debugging that code or maybe building a new one
Hello sir I am Hari Prakash currently working as a physical design engineer and working with synopsys tool(ICC2) I know problem your facing I can help you with that please give me a chance to prove my work in this platform.
Dear sir,
Hoping you are well !
I have wrote many scripts based on Synopsis Custom Compiler with TCL as My graduation project was automating analog layout
let's discuss more about ur project
regards ,
Ammar